It is often desirable for microprocessors and microcomputers (i.e., microprocessors with on-board memory and peripherals) to enter a low-power or Halt mode of operation when not executing instructions.
A Halt mode is entered by placing the device in a "frozen" state in which the crystal oscillator and all clocks are shut down, such that no logic switching occurs. Typically, a microprocessor or microcomputer will have different levels of clocking, with a clock generator creating a master system clock. To enter a Halt mode, the clock generator responds to a HALT command by turning off the system clock that drives the various logic clocks throughout the microcomputer, and then using an internal clock, shuts down the crystal oscillator. At that point, the device is in the Halt mode (frozen) with all logic operations terminated.
After being placed in a Halt mode, the device must transition rapidly to the normal Run operational mode upon the receipt of an interrupt or similar signal from the user or some external circuit. A re-entry or Start transition period is required to re-start the crystal oscillator and recover a stable system clock from the clock generator. That is, tefore any internal processing logic is enabled, the device must complete a Start operation, during which the crystal oscillator is turned on and fed to the clock generator to generate the system clock. This Start mode must last long enough for the oscillator, and therefore the system clock, to stabilize and provide an accurate system clock.
The problem of assuring a stable clock generator output during the Start transition from Halt to the Run operational mode is not the same as the problem of assuring stable clock generator output during power-up. For power-up, a reset pulse initiates a reset sequence and assures stable clock generator output merely by the passage of time. However, for a Halt-to-Run transition, a reset sequence is not required, but rather, it is only necessary to recover the system clock to enable the microcomputer to begin executing instructions as rapidly as possible. The limiting factor in re-entering the Run mode of operation is the recovery of a stable system clock from the clock generator.
Determining when a stable system clock is available from the clock generator during the Start mode depends upon detecting when the re-started crystal oscillator stabilizes and starts beating with the correct frequency and amplitude. Crystal oscillators generally start up with a fairly stable frequency, but with significant amplitude variations. Typically, after a few unsynchronized high-amplitude pulses, the oscillator begins beating at the proper frequency but with a very small amplitude that gradually increases until the oscillator is outputting clock cycles of substantially uniform amplitude (typically approximately between VDD and VSS) at a predetermined frequency.
Heretofore, microcomputers and microprocessors that offer a low-power Halt mode of operation have determined oscillator/clock generator stability, i.e., the duration of the Start mode, by using a large digital counter circuit to count a large number of oscillator clock cycles, after which it is assumed that the oscillator has stabilized and a stable system clock output from the clock generator is available for re-entry into the Run mode. Typically, these devices use a large (more than 10-bit) digital counter capable of counting thousands of clock cycles. Since each bit of the digital counter is normally implemented as a D flip-flop, a digital counter includes multiple D flip-flop circuits, together with associated counter logic.
The digital counter approach to assuring a stable clock generator output after oscillator start-up is disadvantageous for several reasons. The digital counter technique is not entirely reliable because it does not detect oscillator stability, but rather assumes stable operation after a given, albeit large, number of oscillator cycles. As a practical matter, this disadvantage is not too significant because the digital counters are made large enough that stable clock generator operation is achieved during most Start transitions. Nevertheless, the digital counter technique does impact reliability, and in any event, leads to more significant disadvantages. Specifically, in order to have some assurance that stable clock generator operation will be achieved during the Start transition mode, the digital counters count thousands of clock cycles to account for worst case instances of oscillator instability, even though oscillators often stabilize more rapidly than that. Thus, these counters are disadvantageous in terms of delaying unnecessarily (in most cases) the transition to the Run mode. Moreover, a counter of that size is disadvantageous in terms of the amount of logic necessary to implement it.
Accordingly, a need exists for a clock stability circuit for clock-driven digital devices, such as microcomputers and microprocessors, that determines when the device's clock generator is outputting a stable system clock after oscillator start-up, such as during a Start transition from a low-power Halt mode to the normal Run mode of operation. In general, a satisfactory clock stability circuit would actually detect stable oscillator clock operation, thereby assuring a stable clock generator output, and would be implemented with a significantly fewer number of logic elements than required by current digital counter techniques to conserve power and silicon surface area.